Ethane - An Asymmetric File System for Disaggregated Persistent Memory
Innovative file system leveraging disaggregated persistent memory to enhance performance and cost-effectiveness in distributed environments, outperforming modern alternatives by up to 68x.
Expeditious High-Concurrency MicroVM SnapStart in Persistent Memory with Augmented Hypervisor
Innovative system PASS leverages persistent memory for efficient MicroVM SnapStart execution, reducing execution time and doubling concurrency compared to existing solutions.
CrossMapping - Harmonizing Memory Consistency in Cross-ISA Binary Translation
Innovative framework for cross-ISA binary translation, enhancing emulation correctness and performance. Introduces specification tables for unified memory model description and efficient primitive mapping.
FlexMem - Adaptive Page Profiling and Migration for Tiered Memory
Adaptive page profiling and migration system for tiered memory, improving performance through dynamic decision-making and combining profiling methods for enhanced memory management.
Evaluating Chiplet-based Large-Scale Interconnection Networks via Cycle-Accurate Packet-Parallel Simulation
Explore cycle-accurate simulation of large-scale chiplet networks using CNSim, a novel packet-parallel simulator. Gain insights into heterogeneous network design and evaluation for advanced chiplet architectures.
From Core Memory to the Internet - Amazing History of the PDP-11
Explore the fascinating evolution from core memory to PDP-11 computers, tracing DEC's history and the PDP-11's impact on early internet technology in this engaging tech retrospective.
DC-ROMA RISC-V Laptop II Review and Demo
Comprehensive review of DC-ROMA RISC-V Laptop II, showcasing Ubuntu Linux performance, multimedia capabilities, and future potential of RISC-V architecture in mobile computing.
Principled Symbolic Validation of Intel SGX Enclave Runtimes
Explore symbolic validation techniques for Intel SGX enclave runtimes, enhancing security and reliability in trusted execution environments.
OP-TEE is Ready - Let's Use It
Explore OP-TEE's capabilities and practical applications in secure embedded systems with expert guidance from Pengutronix e.K.'s Rouven Czerwinski.
Secure Updates for Memory Constrained XIP Systems
Explore secure update methods for memory-constrained XIP systems, addressing challenges and providing real-world examples for IoT devices running Linux directly from flash memory.
Myth and Truth About Hypervisor-Based Kernel Protector - The Reason Why You Need Shadow-Box
Explore hypervisor-based kernel protection, its limitations, and the need for higher-privilege solutions like Shadow-Box to combat rootkits and kernel exploits effectively.
What Lies Beneath
Explore the journey of Java code from source to hardware execution, uncovering optimization techniques and performance insights along the way.
How to Make Your Electrons Do More in Java - Vector API and TornadoVM
Explore Vector API in Java and TornadoVM for GPU/FPGA computing. Enhance processing power and performance through advanced JVM techniques and native-code tooling.
Deciphering the Mysteries of Human Genomes
Explore the intersection of biology, technology, and medicine in rare genetic disease research. Discover how Python aids in unraveling genomic mysteries and advancing healthcare.
Concurrency and Asynchronous Operations in Databases
Explore database concurrency for scalable solutions, covering threads, synchronization, and essential knowledge for optimal performance.
Efficient CSV Parsing - On the Complexity of Simple Things
Dive into advanced CSV parsing techniques, exploring DuckDB's implementation, parallel algorithms, buffer management, and state machine transitions for handling complex CSV file processing.
I ♥️ Form Controls!
Explore innovative uses of form controls and CSS to create interactive widgets without JavaScript. Learn lateral thinking for lightweight interfaces and discover surprising applications of web technologies.
Extending PyTorch for Custom Compiler Targets - Accelerator Hardware Integration
Discover how to annotate PyTorch code with custom metadata for optimizing model inference on specialized hardware accelerators, focusing on LPU deployment and performance enhancement.
Optimize Your AI Cloud Infrastructure: A Hardware Perspective
Dive into hardware-level optimization techniques for AI cloud infrastructure, exploring GPU clusters, NUMA topology, and performance tuning strategies using H100 clusters and MLPerf benchmarks.
DPDK Graph Library Design and Implementation Details
Dive into DPDK graph library's architecture, implementation specifics, and practical usage patterns for optimizing network packet processing across multiple CPU platforms.
ZXDH DPU Adapter and Its Application in Hardware Acceleration and Networking
Discover ZTE's ASIC-based enhanced data processor with programmable packet processing, hardware offloading, and extensive driver interfaces for virtualization, AI computing, and security applications.