Allegro Means Both Fast and Happy - Coincidence
Explore lesser-known, faster variants of classic sorting algorithms while uncovering surprises and learning to navigate modern complex architectures.
Megahertz, Gigahertz, Registers and Instructions - How Does a CPU Actually Work?
Explore CPU fundamentals, from instruction sets to optimization, covering ARM vs Intel, memory management, and future trends. Gain insights into how processors execute code across various devices.
U2F Zero - Secure Hardware Design, DIY Mass Production, and Amazon Prime
Explore U2F Zero: secure hardware design, DIY production, and Amazon Prime sales. Learn about hardware acceleration, manufacturing challenges, and cost breakdown for this innovative security device.
Tiara - A Scalable and Efficient Hardware Acceleration Architecture for Stateful Layer-4 Load Balancing
Scalable hardware acceleration architecture for stateful layer-4 load balancing, supporting high traffic rates, large concurrent flows, and numerous new connections without traffic pattern assumptions.
ctFS - Replacing File Indexing with Hardware Memory Translation through Contiguous File Allocation for Persistent Memory
Innovative file system design leveraging hardware memory translation for persistent memory, enhancing performance by eliminating indexing overhead and improving efficiency in file operations.
HTMFS - Strong Consistency Comes for Free with Hardware Transactional Memory in Persistent Memory File Systems
Explore hardware-software cooperation for high-performance, strongly consistent persistent memory file systems using Hardware Transactional Memory, overcoming traditional trade-offs between speed and data integrity.
Scalable Memory Protection in the PENGLAI Enclave
Innovative hardware-software design for scalable, dynamic secure memory in enclaves, featuring Guarded Page Tables and Mountable Merkle Trees to enhance protection, performance, and resource utilization.
Write-Optimized Dynamic Hashing for Persistent Memory
Optimizing hash-based indexing for persistent memory: CCEH reduces overhead, guarantees constant lookup time, and ensures failure-atomicity without explicit logging, improving query latency compared to existing techniques.
The nanoPU - A Nanosecond Network Stack for Datacenters
Innovative NIC-CPU co-design accelerating datacenter applications with μs-scale RPCs. Features fast network-to-CPU path, hardware-supported transport and load balancing, achieving 69ns wire-to-wire response time and improved performance.
ArchTM - Architecture-Aware, High Performance Transaction for Persistent Memory
Innovative architecture-aware transaction system for persistent memory, enhancing performance through strategic write management and memory allocation techniques.
Wolverine - Fast, Scalable, and Communication-Efficient Zero-Knowledge Proofs for Boolean and Arithmetic Circuits
Explore fast, scalable zero-knowledge proofs for Boolean and arithmetic circuits, covering applications, existing systems, tradeoffs, and innovative protocols like SVLE and Cotton Bucketing.
fTPM - A Software-Only Implementation of a TPM Chip
Explore software-based TPM implementation using ARM TrustZone, overcoming hardware limitations to provide robust security features for trusted computing in mobile devices.
Crimson - A New Ceph OSD for the Age of Persistent Memory and Fast NVMe Storage
Explore Crimson, a new Ceph OSD designed for low-latency persistent memory and NVMe storage. Learn about its architecture, performance benefits, and future developments in this technical deep dive.
An Empirical Guide to the Behavior and Use of Scalable Persistent Memory
Empirical guide exploring Intel's Optane DIMM behavior, offering insights on performance characteristics and best practices for optimizing persistent memory software in real-world applications.
Optimizing Cost and Performance with Arm64
Explore how Honeycomb.io optimized cost and performance by migrating to arm64 architecture, reducing compute costs by 40% while improving latency, despite challenges in software compatibility and ecosystem complexity.
DNA Data Storage and Near-Molecule Processing for the Yottabyte Era
Explore DNA data storage and near-molecule processing for the yottabyte era, including encoding, decoding, random access, and potential for hybrid electronic/molecular computing systems.
One Glitch to Rule Them All - Fault Injection Attacks Against the AMD Secure Processor
Explore fault injection attacks on AMD's Secure Processor, revealing vulnerabilities in CPU security and discussing implications for system integrity and trust.
Capture This - Real Time Packet Processing With FPGAs
Explore real-time packet processing using FPGAs, focusing on Ethernet connections, FPGA architecture, and implementing network applications with hardware-level optimizations.
HWallet - The Simple Cryptocurrency Hardware Wallet
Explore the creation of a simple cryptocurrency hardware wallet, focusing on hardware acceleration, code optimization, and Bitcoin processing techniques.
Drammer - The Making Of
Exploración técnica del ataque Drammer, que aprovecha la vulnerabilidad Rowhammer en dispositivos Android sin permisos de usuario ni fallas de software. Detalla el proceso de desarrollo y los desafíos enfrentados.
Cache Side Channel Attacks - CPU Design As A Security Problem
Explore CPU cache vulnerabilities and side-channel attacks, their impact on security, and potential mitigations in modern computing environments like cloud and multi-user systems.