RISC-V Cryptography Extensions - Current Status and Future Plans
Explore RISC-V cryptography extensions, their current status, and future developments with insights from Ben Marshall of University of Bristol and PQShield.
Co-Design and Co-Verification of Masked Software Implementations on CPUs
Explore co-design and co-verification of masked software implementations on CPUs, focusing on physical side-channel attacks, hardware/software gaps, and innovative solutions.
Can We Solve Timing Side-Channels in the CPU - TASER 2021
Explore timing side-channel vulnerabilities in CPUs and potential solutions with expert Ronan Lashermes from INRIA. Gain insights into this critical cybersecurity topic.
Running Ubuntu Desktop on ARM-based Laptops
Explore Ubuntu Desktop on ARM laptops: history, challenges, ecosystem, and Lenovo X13s focus. Learn about progress, community efforts, and future plans for Linux on ARM-based desktops.
P2CACHE: Exploring Tiered Memory for In-Kernel File Systems Caching
Explores P2CACHE, a novel in-kernel caching mechanism leveraging persistent memory and DRAM to enhance legacy file systems' performance, durability, and crash consistency without extensive modifications.
Join the RISC-V Revolution - Getting Started with Ubuntu
Explore RISC-V architecture: supported hardware, virtual machines, boot flow, package building, and software availability. Learn about the evolving ISA and its implications for Ubuntu.
Control Flow Integrity on RISC-V
Explore hardware-assisted control flow integrity mechanisms for RISC-V, focusing on shadow stacks and landing pad instructions to enhance program safety and prevent memory-based attacks.
RISC-V Patchwork CI: Setup, Builds, and Testing - Improving Developer Experience
Exploring RISC-V kernel's patchwork CI: setup, builds, tests, limitations, and future plans. Seeking input on improving developer experience and submission quality.
Compute Express Link (CXL) - Overview and Linux Development Status
Explore Compute Express Link (CXL), a new interconnect specification, its features, and Linux community developments. Gain insights into CXL's potential and current progress in Linux integration.
HiSilicon Performance Monitor Control Unit - Offloading PMU Accesses
Offloading PMU accesses to PMCU for non-intrusive CPU monitoring on Kunpeng SoC. Discusses implementation challenges, synchronization issues, and seeks community feedback on use cases and interfaces.
A move_pages() Equivalent for Physical Memory
Proposal for a syscall to migrate physical memory contents between NUMA nodes, exploring integration with mm/migrate.c and potential applications in tiering frameworks.
Developing Continuous eBPF Profiler - From Kernel to Cloud
Explore eBPF profiling for interpreted languages and JIT runtimes, discussing challenges in scalability, uniformity, and integration with cloud-native ecosystems. Learn about edge cases and low-level observability implementation.
xprobes: Hybrid User/Kernel eBPF Probes for Cross-Layer Observability
Explore xprobes, a hybrid eBPF technology combining uprobes and kprobes for enhanced performance diagnostics. Learn how xprobes provide cross-layer visibility, enabling precise attribution of latency to specific functions and system events.
Performance Feature Improvements in RISC-V Linux Kernel
Exploring RISC-V Linux kernel's perf support challenges and upcoming ISA extensions. Discusses implementation issues, event mapping, and user space access to improve performance monitoring capabilities.
Run ILP32 on RV64 ISA - RV64ILP32
Exploring RV64ILP32: advantages, performance comparisons, and implementation across platforms. Demonstrates potential for improved RISC-V hardware performance and cost-effectiveness.
RISC-V IRQ Bypass Implementation for KVM
Explore RISC-V KVM's irqbypass implementation, focusing on AIA and IOMMU specifications, MRIF support, and uAPI proposals for notice MSI delivery. Discuss performance implications and accounting improvements.
RISC-V Support in Android - Current Progress and Challenges
Explore Android's RISC-V integration, covering kernel progress, GKI, extensions, optimizations, and emerging challenges in this processor architecture shift.
Towards a Standardized eBPF ISA - Conformance Testing
Explore the BPF Conformance Suite's role in ensuring cross-runtime compatibility for BPF programs. Learn about its components, applications, and impact on the BPF ecosystem's security and collaboration.
Standardizing CPUID Data for the Open-Source x86 Ecosystem
Proposal to standardize CPUID information for x86 architecture, addressing challenges in feature identification and data redundancy across open-source projects. Aims to improve accuracy and efficiency in CPU feature detection.
RISC-V-Based Sandboxing for Secure and Efficient Software Execution
Explore an efficient RISC-V virtual machine for sandboxed environments, featuring reduced memory usage and JIT compilation for secure software execution.
Supporting Hobbyist-Friendly Open Source Hardware in Zephyr
Explore Zephyr's support for hobbyist-friendly open-source hardware, focusing on Arduino UNO R4, Raspberry Pi Pico, and RISC-V boards. Learn about PIO features, shield compatibility, and ArduinoCore integration.