Tuning Random Forest Hyperparameters with Tidymodels
Learn to optimize random forest models using tidymodels, exploring hyperparameter tuning techniques with San Francisco tree data for improved predictive performance.
Hyperparameter Tuning Using Tidymodels
Explore hyperparameter tuning for random forest models using global food consumption data, enhancing model performance and gaining insights into international dietary patterns.
A New Golden Age for Computer Architecture
Explore the future of computer architecture with insights on RISC, domain-specific languages, and open-source ecosystems. Learn about emerging opportunities in performance, cost, energy, and security.
Ret2spec- Speculative Execution Using Return Stack Buffers
Explore speculative execution security risks, focusing on return stack buffer vulnerabilities and potential countermeasures in modern CPUs.
Concretely-Efficient Zero-Knowledge Arguments for Arithmetic Circuits and Their Application
Explore efficient zero-knowledge arguments for arithmetic circuits, their applications, and novel approaches to MPC-in-the-head protocols, with a focus on improving performance and reducing communication costs.
Boosting Verifiable Computation on Encrypted Data
Explore verifiable computation on encrypted data, covering homomorphic encryption, SNARKs, and polynomial commitments for secure and private delegation of computation.
CHERI and CHERI-RISC-V, by Simon Moore, University of Cambridge
Explore CHERI architecture and its RISC-V implementation, covering hardware principles, software models, and security implications for modern computing systems.
An Overview of Security Topics Within RISC-V, by Helena Handschuh
Overview of RISC-V security topics, including base ISA, privileged architecture, and security task groups. Explores current developments and future directions in RISC-V security.
AES and ISA Extensions
Explore AES encryption and ISA extensions, covering fixed sliced encryption, scalar ISA design, and AES LBB. Learn about tag verification, generation, and SP evaluation.
Current Status of RISC-V Security Mechanisms - Nick Kossifidis, FORTH
Explore RISC-V security mechanisms, including privilege modes, page tables, and control flow integrity, with insights on current status and future proposals.
Primary Memory – Architecture of ROM
Explore ROM architecture, focusing on decoder construction and expansion. Learn to build complex decoders using simpler components and understand their role in computer memory systems.
Cache Replacement Policies - MRU, LRU, Pseudo-LRU, & LFU
Explore cache replacement policies including MRU, LRU, Pseudo-LRU, and LFU. Learn implementation techniques and analyze their effectiveness in managing computer memory.
FlexibleIP - IPv6 Stack for Low-Power Devices Paper Presentation
Explore IPv6 stack optimization for low-power devices, covering cross-layer design, hardware acceleration, header compression, and implementation examples with performance analysis.
Saber on ARM- CCA Secure Module Lattice Based Key Encapsulation on ARM
Explore efficient implementation of Saber, a lattice-based key encapsulation mechanism, on ARM Cortex-M0 and M4 processors, focusing on optimization techniques and performance analysis.
TRRespass- Exploiting the Many Sides of Target Row Refresh
Explore DRAM vulnerabilities and RowHammer attacks with TRRespass, a novel fuzzing technique that exposes weaknesses in Target Row Refresh mitigations, enhancing understanding of hardware security challenges.
Spectre Attacks Exploiting Speculative Execution
Explore speculative execution vulnerabilities in modern processors, their impact on system security, and potential countermeasures to protect against Spectre attacks.
CaSE- Cache-Assisted Secure Execution on ARM Processors
Secure execution framework for ARM processors using TrustZone and Cache-as-RAM to protect sensitive applications against software attacks and cold boot attacks, with minimal performance impact.
Using Hardware Features for Increased Debugging Transparency
Explore hardware-based debugging techniques for enhanced malware analysis transparency, leveraging System Management Mode to overcome limitations of virtualization and emulation methods.
High-Assurance Cryptography in the Spectre Era
Explore cutting-edge cryptography techniques addressing Spectre vulnerabilities, focusing on constant-time implementations and speculative execution semantics for enhanced security.
Systematic Analysis of Randomization-Based Protected Cache Architectures
Explore randomization-based cache protection, analyzing vulnerabilities and introducing Prime+Prune+Probe attack technique for improved security assessment.
Simple High-Level Code for Cryptographic Arithmetic - With Proofs, Without Compromises
Innovative approach to implementing cryptographic arithmetic using high-level code with machine-checked proofs, achieving competitive performance across multiple CPU architectures and prime fields.