CHERI and CHERI-RISC-V, by Simon Moore, University of Cambridge

CHERI and CHERI-RISC-V, by Simon Moore, University of Cambridge

Explore the CHERI (Capability Hardware Enhanced RISC Instructions) architecture and its implementation in RISC-V processors in this informative talk from TASER 2021. Delve into hardware principles, software models, and implementations of CHERI, gaining insights into how this technology enhances security and mitigates exploitation paths. Learn about the fundamental concepts and practical applications of CHERI-RISC-V as presented by Simon Moore from the University of Cambridge.