Gearbox - A Hierarchical Packet Scheduler for Approximate Weighted Fair Queuing
Hierarchical packet scheduler for approximate weighted fair queuing, offering efficient bandwidth allocation and flow isolation in high-speed networks with low complexity and resource usage.
Linux on Open Source Hardware with Open Source Chip Design
Explore open hardware projects for Linux, including BeagleBone and OLinuXino. Learn about RISC-V and free FPGA toolchains for creating libre systems and running Linux on open source chip designs.
Isolation Mechanisms for High-Speed Packet-Processing Pipelines
Explore isolation mechanisms for high-speed packet processing pipelines, focusing on Menshen's approach to enforcing isolation between modules in programmable data planes.
Secret Flaws of In-DRAM RowHammer Mitigations
Unveiling secret flaws in DRAM RowHammer mitigations, exploring Target Row Refresh implementation, and introducing TRRespass: a RowHammer fuzzer for creative hammering patterns to bypass protections.
Capture This - Real Time Packet Processing With FPGAs
Explore real-time packet processing using FPGAs, focusing on Ethernet connections, FPGA architecture, and implementing network applications with hardware-level optimizations.
Hardsploit Project
Hardsploit: A comprehensive toolbox and framework for auditing electronic systems and embedded devices, addressing the growing security challenges in the Internet of Things era.
Information Technology Systems in a Post-Silicon World
Explore post-silicon IT systems, emerging architectures, and AI's impact on InfoSec. Discover how innovation addresses Moore's Law limitations and shapes the future of technology and security.
Liquid Metal - Taming Heterogeneity
Explore IBM's Liquid Metal project for heterogeneous computing, unifying parallel programming paradigms and simplifying development for multicores, GPUs, and FPGAs.
Embedded Systems in Space
Explore satellite systems, space technology, and embedded platforms for orbital missions. Learn about CubeSats, radiation-hardened components, and software reliability in space applications.
FourQ on FPGA - New Hardware Speed Records for Elliptic Curve Cryptography over Large Prime Character
Explore FourQ, a cutting-edge elliptic curve cryptography method, and its implementation on FPGA for unprecedented speed in large prime character systems.
Khronos Sycl Language Framework for C++ Accelerators - Take Advantage of All the MIPS
Explore SYCL, a C++ framework for heterogeneous computing, enabling efficient use of various accelerators. Learn its features, applications, and advantages for high-performance computing and AI/ML development.
What Are FPGAs and How Do They Work
Comprehensive exploration of FPGA technology, covering architecture, programming, and execution processes. Compares FPGAs to traditional processors and discusses their growing role as accelerators in various computing environments.
Boost.Compute - A Library for GPU - Parallel Computing
Explore Boost.Compute, a high-level API for GPU/parallel computing. Learn to write efficient C++ applications for GPUs, FPGAs, and multi-core CPUs using this portable, STL-like library.
Life at a Networking Vendor - Keeping up with the Joneses
Explore the challenges and rewards of working as a kernel developer for a networking hardware vendor, balancing community expectations with internal and external demands.
Intro - CNCF SIG-Runtime
Explore cloud-native runtime technologies, projects, and specialized architectures with CNCF SIG-Runtime. Learn about orchestration, scheduling, and emerging trends in Edge, IoT, AI/ML, and more.
Monitoring 400G Traffic in DPDK Using FPGA-Based SmartNIC with RTE Flow
Discover how to monitor 400G network traffic using FPGA-based SmartNIC and DPDK, featuring hardware acceleration techniques and RTE flow configuration for optimal packet processing performance.
1.2 Tb/s Packet Processing of Radio Telescope Data on GPU
Discover how to process massive radio telescope data streams at 1.2 Tb/s using NVIDIA Grace Hopper GPUs, optimizing packet handling and reducing energy consumption through innovative system architecture.
Addressing Endpoint-Induced Congestion in Scale Out Accelerator Domain
Discover innovative RDMA mechanisms for handling endpoint congestion in accelerator domains, focusing on UDP/IP/Ethernet implementation and efficient congestion control for improved network performance.
CXL-Enabled Heterogeneous Active Memory Tiering: Architecture and Implementation
Explore CXL Type2-based disaggregated memory architecture and how it extends far memory to remote heterogeneous memory using ethernet, featuring intelligent fabric control and memory tiering.
Architectural Challenges and Innovation for Compute Infrastructure Co-Design in Generative AI
Explore architectural solutions for generative AI computing challenges, focusing on heterogeneous computing infrastructure and chiplet-based systems for improved energy efficiency.
Leveraging FPGA-Based Root of Trust for Efficient, Dynamic, and Remote Platform Attestation
Discover how FPGA-based Root of Trust enables secure platform attestation, providing dynamic cryptographic proof of identity and firmware integrity in modern computing systems.