x86x64 Assembly + Python = New CPU Architecture to Rule the World
Explore the fusion of x86/x64 assembly and Python to create innovative CPU architectures, revolutionizing computing paradigms and pushing technological boundaries.
Core Scheduling - Taming Hyper-Threads to Be Secure
Explore CPU vulnerabilities and core scheduling as a solution to keep hyperthreading secure. Learn about implementation, performance impacts, and future directions for this critical security feature.
Impact of Recent CPU Topology Changes
Explore recent CPU topology changes and their impact on Linux systems with insights from experts Dietmar Eggemann and Ionela Voinescu.
Megahertz, Gigahertz, Registers and Instructions - How Does a CPU Actually Work?
Explore CPU fundamentals, from basic operations to advanced optimizations. Learn about different processor architectures, internal workings, and future trends, including security challenges like Meltdown and Spectre.
Hardware Is the New Software - Finding Exploitable Bugs in Hardware Designs
Explore techniques for identifying and exploiting security vulnerabilities in hardware designs, focusing on RISC-V and OR1k CPU architectures using innovative tools and symbolic execution.
AEPIC Leak - Architecturally Leaking Uninitialized Data from the Microarchitecture
Systematic analysis of CPU vulnerabilities, exploring root causes and connections between transient-execution attacks and architectural vulnerabilities. Identifies blank spots in CPU security research.
Secure System Boot Architecture and Protocols for OCP Flashless Boot
Explore the architecture and protocols of OCP Flashless Boot, including system boot processes, PCIe device booting, and future adoption roadmap for secure computing infrastructure.
Beyond CPUs and GPUs - Extending Confidential Computing to DPUs for Enhanced AI Security
Explore how confidential computing extends beyond CPUs and GPUs to DPUs, examining privacy-preserving AI implementations and hardware-based security solutions for third-party infrastructure.
Optical Compute Interconnect: Co-Packaged Optics for AI and Computing Infrastructure
Discover Intel's breakthrough 4 Tbps OCI chiplet technology using Silicon Photonics, enabling next-gen AI compute with high-bandwidth, energy-efficient optical connectivity and integrated laser systems.
Optimizing AI Inferencing with CXL Memory - Memory Tiering Strategies for Enhanced Performance
Explore how CXL-attached memory revolutionizes AI inference systems, enhancing performance and scalability for Large Language Models while optimizing memory bandwidth and reducing latency.
Squeezing a Go Function
Optimize Go functions for peak performance through advanced techniques and best practices. Enhance code efficiency and speed.
Automated Testing of GNU Radio Builds Across Multiple Architectures - GRCon21
Explore automated testing of GNU Radio builds using Buildbot and OpenEmbedded across multiple architectures, with insights on tracking test runs over time.
Extending For_each_lcore for Hardware Topology LCORE - Achieving Higher Performance
Discover how to optimize processor performance through topology-aware LCORE listing, focusing on pkt-distributor, event-dev and pipeline libraries for enhanced payload processing.
Unified Collective Communication - A Library for CPU, GPU, and DPU Integration
Explore the innovative Unified Collective Communication library that seamlessly integrates CPU, GPU, and DPU communication, enhancing performance across diverse computing architectures.
Getting Ready for the Multi-Architectural Universe - Building Flexible DevOps Pipelines
Discover how to transform DevOps pipelines for multi-architecture deployment, covering parallel builds, cross-compilation, and cost-effective infrastructure optimization for ARM-based processors.
Backdoor in the Core - Altering Intel x86 Instruction Set at Runtime
Dive into groundbreaking research on Intel CPU microcode manipulation, exploring techniques for persistent modifications and potential security implications through microcode backdoors in x86 instruction sets.
The Hidden Performance Price of C++ Virtual Functions
Explore the performance impact of C++ virtual functions, understand their underlying mechanisms, and learn optimization techniques to enhance program speed.
Optimizing Away C++ Virtual Functions May Be Pointless
Explore the performance impact of C++ virtual functions, challenging common optimization practices and examining alternatives through modern CPU architecture insights.
A More Intuitive Approach to Optimizing Audio DSP Code - Guiding the Compiler
Discover intuitive techniques for optimizing audio DSP code, focusing on compiler-friendly patterns and efficient benchmarking methods to enhance performance without sacrificing readability.
From Bulb to C# - How Does Computer Work
Explore computer architecture from basic components to modern systems, understanding how hardware and software interact to create powerful computing devices.
C++20's Likely Attribute - Optimizations, Pessimizations, and Unlikely Consequences
Explore C++20's [[likely]] attribute, its impact on optimizations, and potential consequences. Gain insights into branch prediction, performance tuning, and effective benchmarking techniques.