Time Domain Analysis of a Simple PLL
Analyze a simple PLL mathematically and through simulation, focusing on initial frequency error in the time domain.
Course Introduction and Motivation to Phase Locked Loops - Part I
Explore Phase Locked Loops (PLLs), their fundamental concepts, and diverse applications in modern electronic systems. Gain insights into this crucial technology's importance and versatility.
Phase Frequency Detector: Concepts, Detection, and Characteristics
Explore phase frequency detectors: their role in detecting frequency errors, linear range, gain, and frequency transfer characteristics.
Dynamic Logic and Domino Logic - Lecture 6.9
Explore dynamic logic-based NAND/NOR gates, address falling input issues in dynamic inverters, and discover Domino logic as a solution.
Problems in Charge Pump PLL - Reference Spur
Explore reference spur issues in charge pump PLLs and learn techniques like ripple bypass capacitors for suppression.
Noise Analysis in Charge Pump Phase-Locked Loop (CP-PLL): Part II
Explore noise transfer functions, output noise power spectral density, and output jitter calculation in charge pump phase-locked loops (CP-PLLs).
Activity Factor and Estimating Dynamic Power for Combinational Circuit Design - Lecture 9.2
Explore probabilistic methods for estimating activity factors and dynamic power in combinational circuits, analyzing primitive gates and multi-stage designs.
Circuit Level Design of Charge Pump - Part I
Explore source switched charge pump design, charge sharing, clock feedthrough, and output voltage range in this detailed circuit-level analysis.
The Experimental Variogram
Explore the concept of experimental variograms, their calculation, interpretation, and applications in spatial data analysis and geostatistics.
Advanced Topics in Science and Technology of Concrete
Explore cutting-edge concrete science and technology with expert insights from IIT Madras civil engineering professors.
Flexure Behavior - Effect of Compressive Strength on Moment-Curvature Behavior
Explore the impact of compressive strength on moment-curvature analysis in flexural behavior, enhancing understanding of structural mechanics.
MOSFET Scaling and Technology Nodes - Lecture 10.1
Explore MOSFET scaling principles and technology node advancements in semiconductor manufacturing, enhancing understanding of modern transistor design and fabrication.
Extracting Capacitances of 3-NAND Gate for Delay Estimation - Lecture 4.4
Learn to extract capacitances for 3-Nand gate delay estimation and size transistors to match inverter resistances.
Kirchoff's Current and Voltage Laws, and the Incidence Matrix - Lecture 1.2
Explore Kirchoff's Current and Voltage Laws and the Incidence Matrix in electrical engineering, enhancing your understanding of circuit analysis fundamentals.
Bad CMOS Buffer Design Analysis - Part 1
Analyze bad buffer design and its implications in CMOS technology. Learn key concepts for improving circuit performance and reliability.
Logical Effort and Parasitic Delay for Different Gates - Lecture 5.1
Explore delay estimation techniques for various gates, including tristate inverters and multiplexers, to enhance circuit design understanding.
Designing a Linear Regulator - Negative and Positive Feedback
Explore linear regulator design, focusing on negative and positive feedback mechanisms for effective voltage regulation and circuit stability.
Aging of Bituminous Binders and Mixtures - Part III
Explore short-term and long-term aging effects on bituminous materials, including stiffness changes and chemical transformations in binders and mixtures.
Introduction to Environmental Engineering
Explore the role of engineers in mitigating human-induced environmental damage and learn the fundamentals of environmental engineering.
Dead-Time Switching Loss in DC-DC Converters
Explore dead-time switching loss in DC-DC converters, understanding its impact and mitigation strategies for improved power efficiency.
Analog Layout Techniques - Part 2
Explore advanced analog layout techniques, focusing on optimizing circuit performance and minimizing parasitic effects in integrated circuit design.