Extracting Capacitances of 3-NAND Gate for Delay Estimation - Lecture 4.4

Extracting Capacitances of 3-NAND Gate for Delay Estimation - Lecture 4.4

Learn how to extract capacitances for estimating propagation delay in a 3-NAND gate through this informative lecture. Explore the process of calculating both falling and rising delays, and discover techniques for sizing transistors to match the rising and falling resistances of a 2:1 (unit) inverter. Gain valuable insights into delay estimation and transistor sizing for optimal circuit performance.