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    Electrical Engineering

    6,006 courses
    ACE up the Sleeve: Hacking into Apple's New USB-C Controller
    OffensiveCon

    ACE up the Sleeve: Hacking into Apple's New USB-C Controller

    Attacking the Samsung Galaxy A Boot Chain
    OffensiveCon

    Attacking the Samsung Galaxy A Boot Chain

    Booting with Caution: Dissecting Secure Boot's Third-Party Attack Surface
    OffensiveCon

    Booting with Caution: Dissecting Secure Boot's Third-Party Attack Surface

    Open Sesame: Stack Smashing Your Way into Opening Doors
    OffensiveCon

    Open Sesame: Stack Smashing Your Way into Opening Doors

    One SMS to Root Them All: Exposing Critical Threats in Connected Devices
    OffensiveCon

    One SMS to Root Them All: Exposing Critical Threats in Connected Devices

    Signature Estimation and Signal Recovery Using Median of Means
    Conference GSI

    Signature Estimation and Signal Recovery Using Median of Means

    Elmore Delay in Digital CMOS Circuits - Lecture 4.2
    NPTEL-NOC IITM

    Elmore Delay in Digital CMOS Circuits - Lecture 4.2

    Basic Operation of a Phase Locked Loop
    NPTEL-NOC IITM

    Basic Operation of a Phase Locked Loop

    Time Domain Analysis of a Simple PLL
    NPTEL-NOC IITM

    Time Domain Analysis of a Simple PLL

    Course Introduction and Motivation to Phase Locked Loops - Part I
    NPTEL-NOC IITM

    Course Introduction and Motivation to Phase Locked Loops - Part I

    Phase Frequency Detector: Concepts, Detection, and Characteristics
    NPTEL-NOC IITM

    Phase Frequency Detector: Concepts, Detection, and Characteristics

    Dynamic Logic and Domino Logic - Lecture 6.9
    NPTEL-NOC IITM

    Dynamic Logic and Domino Logic - Lecture 6.9

    Problems in Charge Pump PLL - Reference Spur
    NPTEL-NOC IITM

    Problems in Charge Pump PLL - Reference Spur

    Noise Analysis in Charge Pump Phase-Locked Loop (CP-PLL): Part II
    NPTEL-NOC IITM

    Noise Analysis in Charge Pump Phase-Locked Loop (CP-PLL): Part II

    Activity Factor and Estimating Dynamic Power for Combinational Circuit Design - Lecture 9.2
    NPTEL-NOC IITM

    Activity Factor and Estimating Dynamic Power for Combinational Circuit Design - Lecture 9.2

    Circuit Level Design of Charge Pump - Part I
    NPTEL-NOC IITM

    Circuit Level Design of Charge Pump - Part I

    MOSFET Scaling and Technology Nodes - Lecture 10.1
    NPTEL-NOC IITM

    MOSFET Scaling and Technology Nodes - Lecture 10.1

    Extracting Capacitances of 3-NAND Gate for Delay Estimation - Lecture 4.4
    NPTEL-NOC IITM

    Extracting Capacitances of 3-NAND Gate for Delay Estimation - Lecture 4.4

    Kirchoff's Current and Voltage Laws, and the Incidence Matrix - Lecture 1.2
    NPTEL-NOC IITM

    Kirchoff's Current and Voltage Laws, and the Incidence Matrix - Lecture 1.2

    Bad CMOS Buffer Design Analysis - Part 1
    NPTEL-NOC IITM

    Bad CMOS Buffer Design Analysis - Part 1

    Logical Effort and Parasitic Delay for Different Gates - Lecture 5.1
    NPTEL-NOC IITM

    Logical Effort and Parasitic Delay for Different Gates - Lecture 5.1