System-Level Weak Memory Models: The Need for Formalisation, ISA Semantics Integration and Model Diversity
Explore system-level weak memory models, focusing on formalization, ISA semantics integration, and model diversity in computer architecture.
Vectorized Query Execution with SIMD - Lecture 8
Explore advanced vectorized query execution techniques using SIMD for optimized database performance in this comprehensive lecture by Prof. Andy Pavlo.
Next Generation Virtualization-Based Obfuscators
Explores next-gen virtualization-based code obfuscation techniques, focusing on target-specific instruction sets and intertwined VM components to enhance resilience against deobfuscation attacks.
Microwatt Microarchitecture
Detailed exploration of Microwatt, an open-source soft-core implementation of Power ISA, discussing its microarchitecture and design choices influenced by the ISA specifications.
Fedora RISC-V: History, Current Status, and Future Developments
Explore Fedora's journey with RISC-V architecture, from initial porting to current developments and future plans in virtualization and platform standards.
ARM64 SVE Concepts and Integration into DPDK
Explore Arm64's Scalable Vector Extension (SVE) concepts and learn how to integrate this powerful SIMD feature into DPDK libraries for enhanced performance and hardware adaptability.
Computation, Consciousness, and Teleology - Models of Consciousness
Explore the relationship between consciousness, computation, and teleology through the lens of physical systems implementation and mortal computation theory in neural processing.
Open-ISA RISC-V CPU 기반 DSA 개요 및 활용 예시 소개
Discover RISC-V CPU의 차별화된 활용 방안과 DSA 구현 전략을 통해 임베디드 시스템 설계의 새로운 가능성과 ARM 대비 장점을 파악하는 전문가의 통찰력 있는 분석.
Revisiting XSAVE - Lessons from 20 Years of Processor Context State Management
Explore two decades of processor context state management, focusing on XSAVE's evolution and key insights for efficient system design and optimization.
Road to Testing Applications on RISC-V with QEMU and Fedora
Explore RISC-V application testing using QEMU and Fedora, overcoming challenges in VM and container environments without physical hardware.
Automatic Promotion of Helper Functions to TCG Using LLVM
Explore automatic translation of C helper functions to optimized Tiny Code Generators for QEMU using LLVM. Learn about performance improvements and see an interactive demo of C to TCG mappings.
CrossMapping - Harmonizing Memory Consistency in Cross-ISA Binary Translation
Innovative framework for cross-ISA binary translation, enhancing emulation correctness and performance. Introduces specification tables for unified memory model description and efficient primitive mapping.
Backdoor in the Core - Altering Intel x86 Instruction Set at Runtime
Dive into groundbreaking research on Intel CPU microcode manipulation, exploring techniques for persistent modifications and potential security implications through microcode backdoors in x86 instruction sets.
The Beauty of Assembly: Comparing x86_64 and ARM Architectures
Explore assembly differences between x86_64 and ARM architectures, covering fundamentals, examples, and compiler optimization techniques.
RISC-V: Reshaping the Future of Compute
Explore RISC-V's impact on computing's future and its inevitable rise in reshaping the industry landscape.
The Genius of the RISC-V Microprocessor
Explore RISC-V's innovative architecture, its impact on the industry, and how it compares to x86 and ARM processors. Learn about compressed instruction sets, macro-fusion, and micro-operations.