RowHammer, RowPress and Beyond: Can We Be Free of Bitflips Soon? - Stanford Seminar
Explore RowHammer and RowPress vulnerabilities in DRAM chips, their impact on system security, and potential solutions. Gain insights into memory robustness research for reliable and secure systems.
Computing with CXL Memory Devices - Memory Expansion and Computational Offloading
Explore CXL memory devices' role in datacenter optimization, from memory expansion to compute offloading capabilities, with focus on data analytics and telemetry functions.
Memory Technologies Evolution - From DRAM to CXL and Beyond
Explore the evolving landscape of memory technologies, from DRAM and NAND to emerging solutions like MRAM and CXL, understanding their competitive dynamics and future industry implications.
The Key Foundations and Future of Memory Industry Standards
Gain insights into memory industry standards, exploring DDR5 adoption, LPDDR architectures, and future developments in datacenter memory technologies and specifications.
Persistent Memories and Computing Architecture Evolution - From Optane to Future Technologies
Explore emerging memory technologies, their impact on computing architecture, and the legacy of Intel's Optane, including developments in persistent memory, Near/Far Memory paradigms, and chiplet evolution.
Future of Persistent Memory Form Factors and Architectures with CXL
Explore the convergence of storage and memory technologies through CXL protocols, focusing on form factors, management interfaces, and the future of persistent memory architectures.
Introduction to Persistent Memory Technology - Lecture 5T112
Explore the revolutionary world of persistent memory technology, its hardware fundamentals, practical applications, and future impact on storage systems and application performance.
Distributed Random Access Merkledags - Exploring Registry Capabilities
Explore innovative uses of OCI registries, drawing parallels with computer architecture concepts to redefine distributed systems and introduce Distributed Random Access Merkledags.
SIGCOMM 2020 - TEA - Enabling State Intensive Network Functions on Programmable Switches
Explore state-intensive network functions on programmable switches, covering DRAM availability, offloading, migration, and recompiling techniques for enhanced network performance.
P2CACHE: Exploring Tiered Memory for In-Kernel File Systems Caching
Explores P2CACHE, a novel in-kernel caching mechanism leveraging persistent memory and DRAM to enhance legacy file systems' performance, durability, and crash consistency without extensive modifications.
Analyzing and Improving the Scalability of In-Memory Indices for Managed Search Engines
Explore scalability improvements for in-memory indices in managed search engines, comparing compressed and uncompressed indices on DRAM and NVM, and analyzing performance trade-offs.
Flexible and Effective Object Tiering for Heterogeneous Memory Systems
Explore a novel framework for object-level data management in heterogeneous memory systems, evaluating tiering strategies for performance and efficiency on modern Intel platforms.
Cold Boot Attack on DDR2 and DDR3 RAM
Explore cold boot attacks on DDR2 and DDR3 RAM, revealing vulnerabilities in data retention after power loss. Learn techniques, results, and mitigation strategies for this cybersecurity threat.
Exploring the Design Space of Page Management for Multi-Tiered Memory Systems
Explores page management strategies for multi-tiered memory systems, analyzing access locality and tier importance to optimize performance in DRAM and SCM configurations.
How Your DRAM Becomes a Security Problem
Explore DRAM security vulnerabilities and side-channel attacks targeting row buffers, with implications for various devices and systems regardless of software or OS.
On-Chip Randomization for Memory Protection Against Hardware Supply Chain Attacks to DRAM
Explore innovative techniques for safeguarding DRAM against hardware supply chain attacks through on-chip randomization, enhancing memory protection in modern computing systems.
Finding More DRAM
Exploring techniques to optimize DRAM usage across platforms, including proactive memory reclamation and idle memory tracking, to reduce costs without impacting performance.
BBCube 3D - Heterogeneous 3D Integration for TB/s Bandwidth in AI and HPC Applications
Discover groundbreaking BBCube 3D technology for heterogeneous integration, offering enhanced bandwidth and energy efficiency through innovative stacking processes and TSV implementation for AI/HPC applications.
Integrating Composable Memory Solutions into Storage-Intensive Workloads
Explore how CXL memory pooling and expansion techniques optimize performance and reduce TCO for memory-intensive applications like SPARK in data center environments.
CXL 2.0 Use Case - Using Both DDR4 and DDR5 on the Same Server for Memory and Bandwidth Scaling
Explore CXL 2.0 technology's capabilities for integrating DDR4 and DDR5 memory in data centers, focusing on scalable memory expansion and enhanced bandwidth performance for modern computing needs.
Case for DRAM Translation Layer - It's Like FTL but for CXL DRAM
Explore the innovative DRAM Translation Layer technology and its application in CXL DRAM systems, drawing parallels with Flash Translation Layer for enhanced memory management.