Explore a technical conference presentation from the SNIA Compute+Memory+Storage Summit that details a hardware accelerator design for enhancing encryption and decryption performance in SSD storage systems. Learn about the accelerator's integration with RISC-V ISA-based microcontroller SOCs through two distinct configurations - tightly attached and closely attached. Discover how the accelerator implements management, completion, and memory interfaces while supporting multiple processing threads for different storage devices. Understand the design's configurability options, including compute pipes allocation and memory interface channels, as well as its implementation in synthesizable Verilog for SOC integration or FPGA mapping. Gain insights into the accelerator's support for TLS 1.3 cryptographic protocols like AES-128/256, SHA-256/512, and AES-GCM, offering improved throughput and power efficiency compared to firmware-based solutions using RISC-V crypto instruction set extensions.