Explore the rigorous engineering methods applied to develop a security-enhanced processor architecture in this IEEE conference talk. Delve into the use of formal models for the complete instruction-set architecture (ISA) in the design and engineering process of CHERI, a hardware capability-based architecture supporting fine-grained memory protection and scalable secure compartmentalization. Learn about the formalization of key security properties and their verification through mechanized proof. Discover how these methods have been integral to CHERI's development, enabling rapid experimentation and increasing confidence in the design. Gain insights into the potential adoption of CHERI in mass-market commercial processors and its implications for addressing memory safety issues in computing.