Главная
Study mode:
on
1
Introduction
2
ByteAddressable NVM
3
Do we do it in software or hardware
4
Is this something we can do
5
Data Structures
6
XOR Linked Lists
7
Least Significant Bit
8
RedBlack Tree
9
Evaluation Criteria
10
Prior Work
11
Warmup Results
12
XOR Linked List Results
13
Hash Table Results
14
Red Black Trees Results
15
Layer 2 Cache Effects
16
Hash Table Performance
17
Conclusion
18
Real Hardware
19
Questions
Description:
Explore optimization techniques for byte-addressable non-volatile memory (BNVM) systems in this USENIX FAST '19 conference talk. Delve into strategies for reducing bit flipping to improve power consumption and extend memory lifetime in phase change memory (PCM) technologies. Examine modifications to common data structures such as linked lists, hash tables, and red-black trees, achieving up to 3.56× reduction in bit flips compared to standard implementations. Learn about the impact of careful data placement in stack frames and memory allocation on bit flip reduction. Discover how these software-based optimizations can be implemented without hardware modifications or significant performance overhead, making them ideal for BNVM-optimized system design.

Optimizing Systems for Byte-Addressable NVM by Reducing Bit Flipping

USENIX
Add to list