CDXML and JEP30 Models for Chiplet Design and System-Level Verification
Learn about standardized chiplet modeling and verification in this technical presentation that explores how CDXML and JEP30 Part Models enable effective chiplet-based system design. Discover the workflow for designing heterogeneous integrated circuits using chiplet components, including detailed modeling requirements for electrical, mechanical, power, thermal and testability analysis. Examine how the Open Compute Project Foundation's CDXML specification, now adopted as JEDEC JEP30, provides a standardized format for defining and verifying chiplet properties at the system level. Gain insights into system-level testing methodologies that ensure proper integration and functionality of multi-chip assemblies. Master the application of CDXML models in addressing key verification challenges when developing complex chiplet-based systems.