Analyzing Packet Data Flow in Chiplet Based SoCs

Analyzing Packet Data Flow in Chiplet Based SoCs

Learn about packet flow analysis in chiplet-based System on Chips (SoCs) through this technical talk that examines the impact of interconnects on latency. Explore how chiplet architecture differs from monolithic SoCs, with a focus on understanding where additional latencies are introduced in the packet data flow when using Data Plane Development Kit (DPDK). Discover solutions based on Arm product features and industry standards that address these latency challenges. Gain insights into the advantages and considerations of modern chiplet-based CPU designs and their implications for network packet processing.