A High Throughput Gate AES Hardware Architecture by Compressing Encryption and Decryption Datapaths

A High Throughput Gate AES Hardware Architecture by Compressing Encryption and Decryption Datapaths

Explore a 20-minute conference talk from CHES 2016 that presents an innovative approach to AES hardware architecture. Learn about a high-throughput design that compresses both encryption and decryption datapaths, as presented by researchers Rei Ueno, Sumio Morioka, Naofumi Homma, and Takafumi Aoki. Gain insights into advanced cryptographic hardware implementations and their potential impact on improving AES performance in various applications.