Colin O'Flynn
Xilinx HLS- FPGA FIR Filter Design in C in 30 Minutes
1 ratings on Class Central
Design and implement an FPGA FIR filter using Xilinx Vivado High Level Synthesis, covering project setup, C-based design, and FPGA programming in a concise tutorial.
YouTube26 minutesSelf-pacedFree video
Colin O'Flynn
PLIP- ZedBoard-Zynq AES Peripheral in C - Vivado High Level Synthesis
Learn to create an AES peripheral for ZedBoard/Zynq using Vivado HLS. Covers project setup, AES implementation, and system integration for hardware acceleration.
YouTube53 minutesSelf-pacedFree video