Explore a comprehensive guided tour of RISC-V architecture tailored for ARM developers in this 50-minute conference talk. Delve into the fundamentals of RISC-V, including timers, code models, and kernel assembly. Examine development platforms, focusing on Barebox implementation on QEMU and BeagleV. Investigate CPU bootup processes, peripherals, and cache coherency concepts. Compare cache coherency mechanisms between ARM and RISC-V architectures. Analyze specific RISC-V implementations like Allwinner D1 and StarFive JH-7100. Learn about privilege modes, trap-and-emulate techniques, and the Supervisor Binary Interface. Gain insights into clock and reset handling for the JH7100 platform, providing a solid foundation for RISC-V development.