Главная
Study mode:
on
1
Introduction
2
Agenda
3
PCle Evolution
4
Alternate Protocols
5
PCle 60 Specification
6
Backward Compatibility
7
Bandwidth Drivers
8
The virtuous cycle of innovation
9
PCle 60 requirements
10
Probability of failure
11
PAM for signaling
12
Error rate
13
Burst error
14
Retry probability
15
Latency impact
16
Data rate impact
17
Leading edge of technology transition
18
downstream port containment
19
IO virtualization
20
IO security
21
Multiple form factors
22
Cable topology
23
Pool of resources
24
Compliance program
25
Conclusion
26
Answering Question 1
Description:
Watch a 56-minute conference talk exploring the PCIe 6.0 specification and its transformative impact on storage and machine learning applications. Dive deep into the technical advancements of PCIe 6.0, including the implementation of PAM4 signaling, low-latency Forward Error Correction (FEC), and Flit-based encoding that enables doubled data rates of 64 GT/s. Understand how these innovations specifically benefit AI/ML workloads and next-generation cloud data centers through enhanced bandwidth and reduced latency. Learn about backward compatibility, IO virtualization, security features, and various form factors supported by the specification. Gain insights into the future roadmap of PCIe technology and its role in enabling emerging computational demands. Presented by Debendra Das Sharma from UCIe, this technical discussion covers the evolution of PCIe standards, alternative protocols, compliance programs, and practical implementation considerations for storage developers and system architects. Read more

PCIe 6.0 Specification and Beyond - Enabling Storage for Machine Learning Applications

SNIAVideo
Add to list
0:00 / 0:00