Explore a novel machine learning-driven hardware and software co-exploration framework for designing energy-efficient AI accelerators for edge devices in this tinyML Talk. Delve into Dr. Weiwen Jiang's presentation on overcoming the challenge of automating the design of hardware accelerators for neural networks. Learn how this framework simultaneously explores both the architecture search space and the hardware design space to identify optimal neural architecture and hardware pairs, maximizing accuracy and hardware efficiency. Discover how this approach significantly advances the Pareto frontier between hardware efficiency and model accuracy, enabling better design tradeoffs and faster time to market for flexible accelerators designed from the ground up. Gain insights into the importance of this practice for running machine learning on resource-constrained edge devices and its potential to revolutionize the field of tiny machine learning.