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Introduction to Nanoelectronics

CMOS Scaling Theory

Short Channel Effects

Subthreshold Conduction

Drain Induced Barrier Lowering

Channel and Source/Drain Engineering

CMOS Process Flow

Gate oxide scaling and reliability

High-k gate dielectrics

Metal gate transistor

Industrial CMOS Technology

Ideal MOS C-V Characteristics

Effect of non idealities on C-V

MOS Parameter Extraction from C-V Characteristics

MOS Parameter Extraction from I-V Characteristics

MOSFET Analysis, sub-threshold swing “S”

Interface state density effects on “S”. Short Channel Effects (SCE) and Drain Induced Barrier Loweri

Velocity Saturation, Ballistic transport, and Velocity Overshoot Effects and Injection Velocity

SOI Technology and comparisons with Bulk Silicon CMOS technology

SOI MOSFET structures, Partially Depleted (PD)and Fully Depleted (FD) SOIMOSFETs

FD SOI MOSFET: Operation Modes and Threshold Voltages and Electric Fields

Sub-threshold Slope & SCE suppression in FD SOI MOSFET, Volume Inversion and Ultra thin (UTFD) SOI M

Need for MS contact Source/Drain Junction in Nano scale MOSFETs

Rectifying and Ohmic contacts and challenges in MS unction source drain MOSFET Technology

Effect of Interface states and Fermi level pinning on MS contacts on Si and passivation techniques f

Germanium as an alternate to silicon for high performance MOSFETs and the challenges in Germanium Te

Germanium MOSFT technology and recent results on surface passivated Ge MOSFETS

Compound semiconductors and hetero junction FETsfor high performance

GaAs MESFETs: Enhancement and depletion types . Velocity Overshoot effcts in GaAs MESFETs

Hetero-junctions and High Electron Mobility Transistors (HEMT)

Introduction to Nanomaterials

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Description:

Instructors: Prof. Navakanta Bhat, Prof. S. A. Shivashankar and Prof. K. N. Bhat, Centre for Nano Science and Engineering, IIT Bangalore. The objective of this course is to present the state of the art in the areas of semiconductor device physics and materials technology to enable Nanoelectronics. The fundamentals of classical CMOS technology will be discussed and the issue in scaling MOSFET in the sub-100 nm regime will be elaborated. In this context, the need for non-classical transistors with new device structure and nanomaterials will be elucidated. The issues in realizing Germanium and compound semiconductor MOSFET will be presented. Extensive materials characterization techniques will also be discussed, which help in engineering high-performance transistors.

Nanoelectronics: Devices and Materials

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#Engineering #Nanotechnology #Electrical Engineering #Electronics #Nanoelectronics

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