The Needs of IC and Systems Designers are Converging
7
Silicon Stacking The Next IC Packaging Paradigm Change is Here...
8
3D Packaging Versus Silicon Stacking (3DHI)
9
Multi-Chiplet 3D Flow Challenges
10
Top-Level Design Aggregation and Optimization
11
Standards and Co-Design Support
12
Monolithic Die Design To Silicon Stacking Implementation
13
Conclusion
Description:
Save Big on Coursera Plus. 7,000+ courses at $160 off. Limited Time Only!
Grab it
Explore the evolution beyond Moore's Law in this technical presentation that delves into the challenges and opportunities of 3D heterogeneous integration (3DHI) in semiconductor design. Learn why traditional scaling approaches are becoming less economically viable for many semiconductor companies, with factors like reticle limits, yield issues, and astronomical design costs at advanced nodes pushing the industry toward new solutions. Discover how multi-chiplet 3D packaging and More-than-Moore architectures are emerging as alternatives to monolithic designs, offering innovative paths for microelectronics advancement. Examine the complex ecosystem challenges in transitioning from traditional system-on-chip (SoC) to system-in-package (SiP) approaches, including the critical role of EDA tools and design flows in enabling 3DHI implementation. Gain insights into silicon stacking technologies, packaging paradigms, and the convergence of IC and systems design requirements while understanding the technical and practical considerations for engineering teams moving from monolithic to heterogeneous integrated solutions.
Read more
The Challenges of Scaling Beyond Moore's Law - From Monolithic Dies to 3D Heterogeneous Integration