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1
Intro
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Cache Timing Covert Channel
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Disclaimer
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The problem
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I was caught
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I did a video
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Outline of the talk
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Shared resources
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Multiple socket
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Cache line
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Cache timing modulation
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Demo
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Test Program
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Test Results
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BIOS Prefetcher
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Solution
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Userspace
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Physical Address
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KSM
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No synchronization primitive
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Phase lock loop
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CLflush
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The Client
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Monotonic Pulse
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Timers
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Jitter
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Compensation
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Results
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Synchronization
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Recap
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Original experiment
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CPU usage
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Reverse shell example
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Forward error correction
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ReedSolomon
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Reverse Shell
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Disable KSM
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Disable CL Flourish
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Where Counters
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Heuristic
Description:
Explore the intricacies of inter-VM data exfiltration through cache timing covert channels on x86 multi-core systems in this 46-minute conference talk from NorthSec. Delve into the imperfections of shared resource isolation in x86 architecture that enable covert communication between co-located Virtual Machines. Learn how non-privileged applications can establish hidden data transfer channels and reverse shells, bypassing standard access control mechanisms. Discover key concepts and techniques, including cache line encoding/decoding, hardware pre-fetching logic manipulation, exploitation of the 'clflush' instruction, and high-precision inter-VM synchronization. Examine a practical VM-to-VM reverse shell example, bandwidth measurement results, detection methods, and potential countermeasures. Gain insights into shared resources, cache timing modulation, physical address mapping, and forward error correction techniques used in these covert channels.

Inter VM Data Exfiltration - The Art of Cache Timing Covert Channel on x86 Multi-Core

NorthSec
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